1 ps8141c 01/18/01 product features high-speed, to 125 mhz (pi6c180a) low-noise non-inverting 1-18 buffer supports up to four sdram dimms low skew (< 250ps) between any two output clocks i 2 c serial configuration interface multiple v dd , v ss pins for noise reduction 3.3v power supply voltage separate hi-z pin for testing 48-pin ssop package (v) logic block diagram description the pi6c180 is a high-speed low-noise 1-18 noninverting buffer designed for sdram clock buffer applications. pi6c180 can operate up to 100 mhz, whereas pi6c180a is rated at 125 mhz. at power up all sdram output are enabled and active. the i 2 c serial control may be used to individually activate/deactivate any of the 18 output drivers. the output enable (oe) pin may be pulled low to put all outputs in a hi-z state. note: purchase of i 2 c components from pericom conveys a license to use them in an i 2 c system as defined by philips. sdram17 sdram2 sdram1 sdram0 buf_in oe sdata sclock sdram3 i 2 c i/o product pin configuration 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c180 precision 1-18 clock buffer nc 1 nc 2 v dd0 3 sdram0 4 sdram1 5 v ss0 6 v dd1 7 sdram2 8 sdram3 9 v ss1 10 buf_in 11 v dd2 12 sdram4 13 sdram5 14 v ss2 15 v dd3 16 sdram6 17 sdram7 18 v ss3 19 v dd4 20 sdram16 21 v ss4 22 v dd iic 23 sdata 24 nc nc v dd9 sdram15 sdram14 v ss9 v dd8 sdram13 sdram12 48 v ss8 47 oe 46 v dd7 45 sdram11 44 sdram10 43 v ss7 42 v dd6 41 sdram9 40 sdram8 39 v ss6 38 v dd5 37 sdram17 36 v ss5 35 v ss iic 34 sclock 33 32 31 30 29 28 27 26 25 48-pin v
2 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c180 precision 1-18 clock buffer n i pl o b m y se p y ty t qn o i t p i r c s e d 9 , 8 , 5 , 4] 3 - 0 [ m a r d so4 t u p t u o k c o l c 0 e t y b m a r d s 8 1 , 7 1 , 4 1 , 3 1] 7 - 4 [ m a r d so4 t u p t u o k c o l c 1 e t y b m a r d s 6 3 , 5 3 , 2 3 , 1 3] 1 1 - 8 [ m a r d so4 t u p t u o k c o l c 2 e t y b m a r d s 5 4 , 4 4 , 1 4 , 0 4] 5 1 - 2 1 [ m a r d so4 t u p t u o k c o l c 3 e t y b m a r d s 8 2 , 1 2] 7 1 - 6 1 [ m a r d so4 k c a b d e e f r o f e l b a s u s t u p t u o k c o l c m a r d s 1 1n i _ f u bi1 r e f f u b 8 1 - 1 r o f t u p n i 8 3e oi1 k 0 0 1 > a s a h . w o l d l e h n e h w s t u p t u o l l a z - i h w l a n r e t n i r o t s i s e r p u - l l u p 4 2a t a d so / i1 i r o f n i p a t a d 2 k 0 0 1 > a s a h . y r t i u c r i c c w r o t s i s e r p u - l l u p l a n r e t n i 5 2k c o l c so / i1 i n i p k c o l c 2 k 0 0 1 > a s a h . y r t i u c r i c c w r o t s i s e r p u - l l u p l a n r e t n i , 0 2 , 6 1 , 2 1 , 7 , 3 6 4 , 2 4 , 7 3 , 3 3 , 9 2 v 9 - 0 [ d d ]r e w o p0 1s r e f f u b m a r d s r o f y l p p u s r e w o p v 3 . 3 , 2 2 , 9 1 , 5 1 , 0 1 , 6 3 4 , 9 3 , 4 3 , 0 3 , 7 2 v 9 - 0 [ s s ]d n u o r g0 1s r e f f u b m a r d s r o f d n u o r g 3 2v c i i d d r e w o p1 i r o f y l p p u s r e w o p v 3 . 3 2 y r t i u c r i c c 6 2v c i i s s d n u o r g1 i r o f d n u o r g 2 y r t i u c r i c c 8 4 , 7 4 , 2 , 1c nd e v r e s e r4 s t c e n n o c o n . n o i t a c i f i d o m e r u t u f r o f d e v r e s e r product pin description oe functionality pi6c180 i 2 c address assignment notes: 1. used for test purposes only 2. buffers are non-inverting pi6c180 serial configuration map byte0: sdram active/inactive register (1 = enable, 0 = disable) note: inactive means outputs are held low and are disabled from switching. e o] 7 1 - 0 [ m a r d se t o n 0z - i h1 1n i _ f u b2 6 a5 a4 a3 a2 a1 a0 aw / r 1101001 0 t i b# n i pn o i t p i r c s e d 7 t i b8 1 7 m a r d s ) e v i t c a n i / e v i t c a ( 6 t i b7 1 6 m a r d s ) e v i t c a n i / e v i t c a ( 5 t i b4 1 5 m a r d s ) e v i t c a n i / e v i t c a ( 4 t i b3 1 4 m a r d s ) e v i t c a n i / e v i t c a ( 3 t i b9 3 m a r d s ) e v i t c a n i / e v i t c a ( 2 t i b8 2 m a r d s ) e v i t c a n i / e v i t c a ( 1 t i b5 1 m a r d s ) e v i t c a n i / e v i t c a ( 0 t i b4 0 m a r d s ) e v i t c a n i / e v i t c a (
pi6c180 precision 1-18 clock buffer 3 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2-wire i 2 c control the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c180 is a slave receiver device. it can not be read back. sub addressing is not supported. all preceding bytes must be sent in order to change one of the control bytes. every bite put on the sdata line must be 8-bits long (msb first), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclock is low. exceptions: a high to low transition on sdata while sclock is high indicates a start condition. a low to high transition on sdatawhile sclock is high is a stop condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low= write to addressed device). if the devices own address is detected, pi6c180 generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. following acknowledgement of the address byte (d2), two more bytes must be sent: 1. command code byte, and 2. byte count byte. although the data bits on these two bytes are dont care, they must be sent and acknowledged. byte1: sdram active/inactive register (1 = enable, 0 = disable) byte2: optional register for possible future requirements (1 = enable, 0 = disable) t i b# n i pn o i t p i r c s e d 7 t i b5 4) e v i t c a n i / e v i t c a ( 5 1 m a r d s 6 t i b4 4) e v i t c a n i / e v i t c a ( 4 1 m a r d s 5 t i b1 4) e v i t c a n i / e v i t c a ( 3 1 m a r d s 4 t i b0 4) e v i t c a n i / e v i t c a ( 2 1 m a r d s 3 t i b6 3) e v i t c a n i / e v i t c a ( 1 1 m a r d s 2 t i b5 3) e v i t c a n i / e v i t c a ( 0 1 m a r d s 1 t i b2 3) e v i t c a n i / e v i t c a ( 9 m a r d s 0 t i b1 3) e v i t c a n i / e v i t c a ( 8 m a r d s t i b# n i pn o i t p i r c s e d 7 t i b8 2) e v i t c a n i / e v i t c a ( 7 1 m a r d s 6 t i b1 2) e v i t c a n i / e v i t c a ( 6 1 m a r d s 5 t i b) d e v r e s e r ( 4 t i b) d e v r e s e r ( 3 t i b) d e v r e s e r ( 2 t i b) d e v r e s e r ( 1 t i b) d e v r e s e r ( 0 t i b) d e v r e s e r ( maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ............................................................. C65c to +150c ambient temperature with power applied .............................. C0c to +70c 3.3v supply voltage to ground potential .............................. C0.5v to +4.6v dc input voltage .................................................................... C0.5v to +4.6v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. supply current (v dd = +3.465v, c load = max.) l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. p y t. x a ms t i n u i d d t n e r r u c y l p p u sz h m 0 = n i _ f u b3 a m i d d t n e r r u c y l p p u sz h m 6 6 . 6 6 = n i _ f u b0 3 2 i d d t n e r r u c y l p p u sz h m 0 . 0 0 1 = n i _ f u b0 6 3
4 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c180 precision 1-18 clock buffer sdram clock buffer operating specification ac timing dc operating specifications (v dd = +3.3v 5%, t a = 0c - 70c) l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. x a ms t i n u e g a t l o v t u p n i v h i e g a t l o v h g i h t u p n iv d d 0 . 2v d d 3 . 0 + v v l i e g a t l o v w o l t u p n iv s s 3 . 0 -8 . 0 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < d d 5 -5 +a m v d d % 5 v 3 . 3 = ] 9 - 0 [ v h o e g a t l o v h g i h t u p t u oi h o a m 1 - =4 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 c t u o e c n a t i c a p a c n i p t u p t u o6 f p c n i e c n a t i c a p a c n i p t u p n i5 l n i p e c n a t c u d n i n i p7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c l o b m y sr e t e m a r a ps n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 2 =4 5 - a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 3 1 . 3 =6 4 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 0 . 1 =4 5 i x a m l o t n e r r u c n w o d - l l u pv t u o v 4 . 0 =3 5 t h r m a r d s e t a r e g d e e s i r t u p t u o y l n o m a r d s % 5 v 3 . 3 v 4 . 2 - v 4 0 @ 5 . 14 s n / v t h t m a r d s e t a r e g d e l l a f t u p t u o y l n o m a r d s % 5 v 3 . 3 v 4 . 0 - v 4 . 2 @ 5 . 14 l o b m y sr e t e m a r a p a 0 8 1 c 6 i p s t i n u z h m 6 6z h m 0 0 1z h m 3 3 1 . n i m. x a m. n i m. x a m. n i m. x a m t p k d s d o i r e p k l c m a r d s0 . 5 15 . 5 10 . 0 15 . 0 15 . 78 . 7 s n t h k d s e m i t h g i h k l c m a r d s6 . 53 . 30 . 1 t l k d s e m i t w o l k l c m a r d s3 . 51 . 30 . 1 t e s i r d s e m i t e s i r k l c m a r d s5 . 10 . 45 . 10 . 45 . 10 . 4 s n / v t l l a f d s e m i t l l a f k l c m a r d s5 . 10 . 45 . 10 . 45 . 10 . 4 t h l p y a l e d p o r p h l r e f f u b m a r d s0 . 10 . 50 . 10 . 50 . 10 . 5 s n t l h p y a l e d p o r p l h r e f f u b m a r d s0 . 10 . 50 . 10 . 50 . 10 . 5 t l z p t , h z p y a l e d e l b a n e r e f f u b m a r d s0 . 10 . 80 . 10 . 80 . 10 . 8 t z l p t , z h p y a l e d e l b a s i d r e f f u b m a r d s0 . 10 . 80 . 10 . 80 . 10 . 8 e l c y c y t u dv 5 . 1 t a d e r u s a e m5 45 55 45 55 45 5% t w k s d s w e k s t u p t u o o t t u p t u o m a r d s0 5 20 5 20 5 2s p
pi6c180 precision 1-18 clock buffer 5 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1.5v 1.5v t phl t plh 1.5v 1.5v input waveform output waveform output buffer test point 2.4 1.5 0.4 tsdkh tsdkp 3.3v clocking interface (ttl) tsdkl t sdfall t sdrise test load figure 1. clock waveforms notes: 1. maximum rise/fall times are guaranteed at maximum specified load. 2. minimum rise/fall times are guaranteed at minimum specified load. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 w resistor in parallel. minimum and maximum expected capacitive loads design guidelines to reduce emi 1. place series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10pf. series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of vias of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. k c o l cd a o l . n i md a o l . x a ms t i n us e t o n m a r d s0 20 3f pn o i t a c i f i c e p s m m i d m a r d s
6 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c180 precision 1-18 clock buffer pcb layout suggestion note: this is only a suggested layout. there may be alternate solutions depending on actual pcb design and layout. as a general rule, c1-c11 should be placed as close as possible to their respective v dd . recommended capacitor values: c1-c11 .............. 0.1 m f, ceramic c12 ................. 22 m f c1 c2 c3 c4 c5 c6 ferrite bead c11 c10 c8 c7 c9 vcc c12 22uf via to gnd plane via to vdd plane void in power plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vdd vss vdd vss vdd vss vdd vss vdd vss vdd vdd vss vdd vss vdd vss vdd vss vdd vss vss
pi6c180 precision 1-18 clock buffer 7 ps8141c 01/18/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 0.20 0.51 1.01 0.25 0.381 0.635 .008 .008 .016 0-8? 0.20 0.40 .110 2.79 .010 gauge plane .02 .04 .015 .025 x 45? .025 bsc 0.635 .291 .299 x.xx x.xx denotes dimensions in millimeters 7.39 7.59 .395 .420 10.03 10.67 .620 .630 15.75 16.00 .008 .0135 0.20 0.34 1 48 nom. max 48-pin ssop package data table of dimensions ordering information sdram 22 w 18 ci pi6c180 sdram dimm spec. 100/66 mhz clock from chipset figure 2. design guidelines y d o b) h t d i w ( e) h t g n e l ( d) t h g i e h ( a) h c t i p n i p - o t - n i p ( e s n i p 8 4. n i m1 9 2 . 00 2 6 . 05 9 0 . 05 2 0 . 0 ) l i m 0 0 3 (. x a m9 9 2 . 00 3 6 . 00 1 1 . 0- n / pn o i t p i r c s e d v 0 8 1 c 6 i pe g a k c a p p o s s n i p - 8 4 v a 0 8 1 c 6 i pe g a k c a p p o s s n i p - 8 4
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